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XR16M890
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.1
CPU Interface
There are 3 CPU interfaces that can be selected on the XR16M890. They are the Intel, Motorola and VLIO
bus interfaces. Note: no clock (crystal or external clock) is required for data bus transactions. Each bus cycle
is asynchronous.
1.1.1
Intel bus interface (16 mode)
The Intel bus interface consists of 8 data bits, 3 address lines and 3 control signals (CS#, IOR# and IOW#) for
data bus read/write transactions. In this mode, the interrupt output (INT) is active high. A typical data bus
interconnection is shown in Figure 4 .
F IGURE 4. XR16M890 T YPICAL I NTEL D ATA B US I NTERCONNECTION
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
U A R T _ IO R #
U A R T _ IO W #
UART_CS#
U A R T _ IN T
S L E E P /P W R D N
U AR T_R ES ET
1.1.2
Motorola bus interface (68 mode)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IO R #
IO W #
CS#
IN T
S L E E P /P W R D N
RESET
VC C _B U S
1 6 /6 8 #
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
R I#
V L IO _ E N
GND
VCC_BUS
S e ria l T ra n s c e ive rs o f
R S -2 3 2
R S -4 8 5
R S -4 2 2
O r In fra re d
The Motorola bus interface is similar to the Intel bus interface. This interface consists of 8 data bits, 3 address
lines, but only 2 control signals (CS# and R/W#) for data bus read/write transactions. In this mode, the
interrupt output (IRQ#) is an open-drain and active low. A typical data bus interconnection is shown in
Figure 5 .
F IGURE 5. XR16M890 T YPICAL M OTOROLA D ATA B US I NTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
VCC_BUS
TX
RX
DTR#
VCC_BUS
S e ria l T ra n s c e iv e rs o f
A0
A1
A2
R /W #
U AR T_C S #
U A R T _ IR Q #
S L E E P /P W R D N
vcc
VCC
A0
A1
A2
IO R #
IO W #
CS#
IR Q #
S L E E P /P W R D N
RTS#
CTS#
DSR#
CD#
R I#
1 6 /6 8 #
V L IO _ E N
GND
R S -2 3 2
R S -4 8 5
R S -4 2 2
O r In fra re d
UART_RESET#
9
RESET#
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